libc/atomic: refactor inline arch atomics, add atomic_ptr_t/atomic64/cmpxchg_release_acquire - #20043
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zhangyu-duck wants to merge 6 commits into
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libc/atomic: refactor inline arch atomics, add atomic_ptr_t/atomic64/cmpxchg_release_acquire#20043zhangyu-duck wants to merge 6 commits into
zhangyu-duck wants to merge 6 commits into
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Add atomic_ptr_t that maps to atomic_t on 32-bit platforms and atomic64_t on 64-bit platforms based on UINTPTR_MAX. All atomic_ptr_xx operations (set, read, add, sub, and, or, xor, xchg, cmpxchg, try_cmpxchg with memory order variants) are mapped to the corresponding atomic_xx or atomic64_xx macros accordingly. Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
When CONFIG_LIBC_ATOMIC_ARCH is selected, atomic.h includes arch/atomic.h which provides static inline atomic_*_4 operations using arch-specific helpers. This eliminates function call overhead for NuttX atomic API. For Tricore, the inline functions use hardware helpers (tricore_atomic_swap, tricore_atomic_cmpswap) implemented with inline assembly (swap.w, cmpswap.w), avoiding the iLLD dependency. The arch_atomic.c retains __atomic_*_4 symbols with external linkage for GCC libatomic ABI compatibility. Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
1. Add include/nuttx/lib/arch_atomic.h with inline atomic_*_4/8 and
__sync_*_{1,2,4,8} operations using IRQ disable/enable or hwspinlock
under CONFIG_LIBC_ATOMIC_IRQ / CONFIG_LIBC_ATOMIC_HWSPINLOCK.
2. Include the new header from include/nuttx/atomic.h so the NuttX
atomic API becomes inline (no function call overhead).
3. Reduce libs/libc/machine/arch_atomic.c to only export __atomic_*
and __sync_* symbols for GCC libatomic ABI; delete the local
arch_atomic.h and arch_atomic64.c (superseded); update Make.defs
and CMakeLists.txt accordingly.
4. Fix a pre-existing race in SYNC_*_FETCH macros where the return
value was read from shared memory after releasing the lock; now
captured in a local variable before unlocking.
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
1. Add ARCH_HAVE_ATOMIC_4 guard in arch/tricore/include/atomic.h so
the tricore arch declares which sizes have hardware atomic support.
2. Extend include/nuttx/lib/arch_atomic.h to #undef arch overrides
and provide IRQ-based inline fallback for sizes the arch does not
support, so generic code covers all {1,2,4,8} sizes uniformly.
3. Update libs/libc/machine/arch_atomic.c to gate per-size symbol
export on ARCH_HAVE_ATOMIC_X and 64-bit on UINTPTR_MAX > UINT32_MAX;
delete libs/libc/machine/tricore/arch_atomic.c (now merged into
the generic machine/arch_atomic.c).
4. Drop tricore-specific arch_atomic.c references from
libs/libc/machine/tricore/{Make.defs,CMakeLists.txt}.
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
1. Add atomic_cmpxchg_release_acquire and atomic_try_cmpxchg_release_acquire for 32-bit (atomic_compare_exchange_4) using RELEASE on CAS success. 2. Add 64-bit counterparts atomic64_cmpxchg_release_acquire and atomic64_try_cmpxchg_release_acquire (atomic_compare_exchange_8). 3. Add pointer-width aliases atomic_ptr_cmpxchg_release_acquire and atomic_ptr_try_cmpxchg_release_acquire for both 64-bit and 32-bit pointer configurations, expanding the existing ptr_*_cmpxchg family. 4. Use ACQUIRE on CAS failure so the retry path re-acquires visibility of updates from other threads, matching the ordering used by DPDK RTS ring tail-commit CAS. Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
libc/machine/arch_atomic64.c implementing atomic_*_8 on a single spinlock. All helpers are weak_function so an arch with native 64-bit support overrides at link time Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
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Summary
Refactor NuttX's atomic operations to support inline arch-specific implementations, add new atomic types/variants, and provide 64-bit atomic support via spinlock.
Commits
include/atomic: add atomic_ptr_t type and operations— add pointer-width atomic type and operationslibc/atomic: support inline arch atomic for tricore— tricore inlineatomic_*_4viaswap.w/cmpswap.wlibc/atomic: support inline arch atomic for generic IRQ path— generic IRQ/hwspinlock-based atomic path for archs without hardware atomicslibc/atomic: merge tricore arch_atomic.c into machine/arch_atomic.c— unify tricore atomic implementation into the genericmachine/arch_atomic.cinclude/atomic: add cmpxchg_release_acquire memory order variant— new cmpxchg memory order matching DPDK RTS ring tail-commit orderinglibc: realize atomic64 via a spinlock helper— 8-byte atomic symbols on a single spinlock for archs without native 64-bit supportImpact
atomic_ptr_ttype: pointer-width atomic type and operations (commit 1)atomic_*_4inlined viaswap.w/cmpswap.whardware instructions, no function call overhead (commit 2)arch_atomic.cmerged into genericmachine/arch_atomic.c(commit 4)atomic_cmpxchg_release_acquireandatomic_try_cmpxchg_release_acquirefor 32/64/pointer-width (commit 5)atomic_*_8,__atomic_*_8,sync_*_8,__sync_*_8symbols provided vialibs/libc/machine/arch_atomic64.con a single spinlock (g_atomic64_lock), usingspin_lock_irqsavefor SMP correctness and local ISR safety; all helpersweak_functionso archs with native 64-bit support can override at link time (commit 6)