[asterick]

Summary

Four small, independent correctness fixes (stacked on #51 — retarget to main after it merges):

1. RTC prescaler (rtc.cc): prescale -= prescale zeroed the counter instead of subtracting the 0x8000 overflow threshold. Honest severity: latent, not symptomatic — osc1 reaches RTC::clock one tick at a time, so the remainder at crossing is always zero and both forms coincide today. Verified by A/B: zero divergence on baselines and on 3 commercial ROMs × 30 s. It would silently lose time the moment osc1 delivery was ever batched. The harness exercise now starts the RTC and the log line prints rtc=value+prescale, so the subsystem is regression-covered going forward (baselines regenerated for the new column).
2. libretro savestates (libretro.cc): retro_unserialize() copied the state then returned false — every savestate load reported failure to the frontend. Now returns true.
3. Breakpoints are a Set<number> instead of an array — the running loop did an indexOf per executed instruction.
4. npm scripts chain with && instead of ; — a failed core build no longer lets vite build "succeed" with a stale wasm. (CI's stale comment about this updated too.)

Verification

• RTC A/B (old vs fixed code): byte-identical exercise baselines and ROM runs — confirming both the fix's safety and its latent-only severity
• Breakpoints driven in the browser: set/set/clear via disassembly clicks, counts correct; running with a breakpoint on the BIOS idle loop halts immediately
• libretro .so builds; npm run check, wasm core build, and make -C core/test check all clean

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