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1. spi-fpga-core spi-fpga-core Public

   SPI master+slave IP core in SystemVerilog. All 4 modes (CPOL/CPHA), parametrizable bit-width, FIFO, optional AXI4-Lite wrapper.

   SystemVerilog 3

2. keccak-fpga-core keccak-fpga-core Public

   Keccak/SHA-3 family IP core in SystemVerilog. FIPS-202 + Ethereum Keccak-256 compliant, dual-licensed.

   SystemVerilog 2

3. aes128-fpga-core aes128-fpga-core Public

   AES-128 IP core in SystemVerilog. FIPS-197 compliant, dual-licensed, with secure (DPA-resistant) and pipelined variants.

   C++ 1

4. axi4lite-slave-fpga-core axi4lite-slave-fpga-core Public

   AXI4-Lite slave parametrizable IP core in SystemVerilog. ARM AMBA AXI compliant, with YAML to SV+C register-map generator.

   SystemVerilog 1

5. pid-fpga-core pid-fpga-core Public

   Discrete-time PID controller IP core in SystemVerilog. Anti-windup, output clamping, D-on-PV. For drones, motor control, process control.

   SystemVerilog 1

6. fir-filter-fpga-core fir-filter-fpga-core Public

   Parametric FIR filter IP core in SystemVerilog. Transposed direct-form, AXI4-Stream, bit-exact vs scipy.signal.lfilter. For DSP/SDR/audio/ML.

   C++ 1 1