An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
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Updated
Feb 14, 2022 - C
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
QKeras: a quantization deep learning library for Tensorflow Keras
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
Research and Materials on Hardware implementation of Transformer Model
Convolutional accelerator kernel, target ASIC & FPGA
Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.
Small-scale Tensor Processing Unit built on an FPGA
OpenGL 1.x implementation for FPGAs
Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design contest.
BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.
Basic OpenGL 1.x implementation for small FPGAs (like iCE40UP5K)
OPAE porting to Xilinx FPGA devices.
Lenet for MNIST handwritten digit recognition using Vivado hls tool
Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
This project implements a convolution kernel based on vivado HLS on zcu104
A Configurable Deep Neural Network Accelerator built from scratch on the Basys3 FPGA
FPGA-based hardware acceleration for dropout-based Bayesian Neural Networks.
Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs
Implementation of a binary search tree algorithm in a FPGA/ASIC IP
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