xsim

Vivado MCP server — 让 Claude Code / Cursor / Codex 驱动本地 FPGA 全流程。30 个精选工具、8 个证据驱动 Prompt、doctor 环境自检、GUI/Tcl/attach 会话，以及时序和 CRITICAL WARNING 中文诊断。

PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities

USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL

10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL

Convert Vivado/VCD/XSim WDB and WCFG waveform databases directly to VCD, CSV, JSON and Excel. GUI, batch conversion, signal filtering and radix controlls.

Vivado Simulator (XSim) xvlog/xvhdl plugin for SublimeLinter. Linting for Verilog/SystemVerilog and VHDL.

Logic Expression Compiler, with Logic Minimization, to NAND/NOR Implementation

This project implements AXI-based matrix multiply accelerator.

A verified four-stage RV32I pipeline with parameterized L1 instruction/data caches, XSim regression tests, and portable Vivado flows.

This repository showcases my hands-on SystemVerilog UVM verification using Xilinx Vivado XSIM, focusing on real-world RTL verification, debugging, coverage, and regression scenarios.

Simple UVM example with Altair (Metrics) DSim and Vivado xsim

UVM 1.2 functional verification environment for ARMv8-M PACBTI, TrustZone, privilege faults, and AHB-Lite behavior

HSpecID-X: A Hyperspectral Pixel Classifier Accelerator for X-HEEP

SystemVerilog AXI4-Lite protocol verification environment featuring a 5-channel monitor, associative-array scoreboard, 13 SVA assertions, functional coverage closure, back-pressure testing, and negative protocol testbench.